1. Field of the Invention
The present invention relates to a test apparatus, a phase adjusting method and a memory controller. More specifically, the present invention relates to a test apparatus for testing a memory-under-test, a phase adjusting method for adjusting timing of an output signal outputted from the memory-under-test and a strobe signal, and a memory controller for controlling writing/reading data to/from the memory.
2. Related Art
FIG. 12 shows a configuration of a conventional test apparatus 10. The test apparatus 10 is provided with variable delay circuits 12, 14, 22, 24, 32 and 42, SR latches 16 and 26, drivers 18 and 28, level comparators 30 and 40 and timing comparators 34 and 44.
The SR latch 16 generates and outputs a test pattern signal based on a set signal delayed by the variable delay circuit 12 and a reset signal delayed by the variable delay circuit 14 and supplies the signal to a memory-under-test 50 via the driver 18. The SR latch 26 generates and outputs a test pattern signal based on a set signal delayed by the variable delay circuit 22 and a reset signal delayed by the variable delay circuit 24 and supplies the signal to the memory-under-test 50 via the driver 28. The timing comparator 34 receives an output signal from the memory-under-test 50 via the level comparator 30 and samples an output value based on a strobe signal delayed by the variable delay circuit 32. The timing comparator 44 receives an output signal from the memory-under-test 50 via the level comparator 40 and samples an output value based on a strobe signal delayed by the variable delay circuit 42.
Then, a logical comparator compares the output values sampled by the timing comparators 34 and 44 with an expected value generated in advance. The test apparatus 10 judges acceptability of the memory-under-test 50 based on the comparison result of the logical comparator.
Before executing the test of the memory-under-test 50, the following phase adjustment is made in the test apparatus 10. At first, the delays of the variable delay circuits 12 and 14 are set so that phases of the test pattern signals outputted from the drivers 18 and 28 are phased at terminals of the memory-under-test 50. Still more, the delays of the variable delay circuits 32 and 42 are set so that the output signals outputted from the memory-under-test 50 in the same phase are accurately sampled by the timing comparators 34 and 44.
Since the applicant of the invention is unaware of existence of any document concerning to the prior art at the present time, description concerning to the prior art document will be omitted here.
In the phase adjustment in the conventional test apparatus 10, the delays of the variable delay circuits 12 and 14 are set so that the phases of the test pattern signals outputted from the drivers 18 and 28 are phased at the terminals of the memory-under-test 50. Therefore, in testing the memory-under-test 50 that operates at very high frequency, it becomes difficult to correctly sample the output signal outputted from the memory-under-test 50 due to dispersion of output timing of the output signal of the memory-under-test 50 and to dispersion of timing of the timing comparators 34 and 44 for receiving the strobe signals. Still more, it takes an enormous amount of time, thus dropping the throughput of the test, if the phase adjustment of the strobe signal is to be made every time when the memory-under-test 50 is mounted to suppress the dispersion of the timing of the timing comparators 34 and 44 for receiving the strobe signal.